NVIDIA公司ASIC Intern的筆試
昨天去參加nVIDIA公司ASIC Intern的筆試,hr沒有告訴我具體地點,一開始走錯了地方,去了春曉路122弄34號4號樓,問了下才知道那裡是nVIDIA的Physical Design部門,讓我去金科路2966號,結果又走了半個多小時才找到,幸好我去的早,要不肯定遲到了,哎,我受傷未愈的腳啊。。。
下午3點準時開始,題量不大,一共6道,也不是很難,第一題是時序問題,第二題寫Verilog程式碼實現同步復位和非同步復位的觸發器,後面詳細說它,第三題畫狀態圖,第四題估算計算結果所需的最小位寬,第五題給條件求FIFO所需的最小長度,第六題是4個人過橋問題,所需最短的時間,很常見了,可我還是想了好一會。
現在還讓我很鬱悶的事情是,居然第二題做錯了,越想越鬱悶,這個錯誤將讓我錯失這次我很看重的機會,傷心死了。。。
我居然將同步復位的Flip-flop寫成非同步復位的Flip-flop,然後你可想而知,寫非同步復位的Flip-flop時我就不知道怎麼寫了,寫成
assign = (!Reset)? 0: data_input;
我當時也很納悶,但我的確不知道應該怎麼寫,我的理解中同步電路是時鐘沿觸發,非同步電路是電平觸發,而平時設計中都直接用非同步復位的Flip-flop,還以為那就是同步復位的Flip-flop(當然這些都是我今天查閱一本書後才知道自己錯在哪裡的)。決定在這裡完整的寫一下這兩個模組,利己利人。
// synchronous reset flip-flop
module syn_flipflop(clk, Reset, data_input, data_output);
input clk, Reset, data_input;
output reg data_output;
always @(posedge clk)
begin
if(!Reset)
data_output <= 0;
else
data_output <= data_input;
end
endmodule
//asynchronous reset flip-flop
module asyn_flipflop(clk, Reset, data_input, data_output);
input clk, Reset, data_input;
output reg data_output;
always @(posedge clk or negedge Reset)
begin
if(!Reset)
data_output <= 0;
else
data_output <= data_input;
end
endmodule
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